1. Field of the Invention
This invention relates to a method for eliminating the latch-up effect in semiconductor devices and integrated circuits and particularly to irradiating integrated circuits with high energy ions with molecular weight of at least one ion.
2. Description of the Prior Art
Latch-up effects are well known in semiconductor devices and integrated circuits where upon latch-up a low resistance path is created through successively doped regions of a pnpn four-layer structure. A parasite pnpn structure occurs in bipolar and complementary metal oxide semiconductor (CMOS) integrated circuits. Integrated circuits are formed as a consequence of forming a number of bipolar or MOS transistors in a common substrate. Individual transistors are isolated by diffusions to form separate regions or tubs in the substrate. Protective diodes are also diffused into a diffusion tub or substrate. One side of the diode is coupled to a gate input to protect the gate electrode from overvoltage. The diffusion tubs and protective diodes provide additional pn junctions.
The four-layer structure having adjacent regions of pnpn doped material forms an unintended thyristor or silicon-controlled rectifier (SCR) which may also be viewed as a pnp bipolar transistor coupled to an npn transistor where the base of the pnp transistor is coupled to and forms the collector of the npn transistor, and the emitter of the pnp transistor is coupled to and forms the base of the npn transistor. The four-layer structure or thyristor is a bistable device which can be triggered from its high resistance state to a conducting state by passing current into the p region or the base of the npn transistor causing the npn transistor to turn on which, in turn, causes the pnp transistor to conduct, resulting in current flow through the entire four-layer pnpn structure. The four-layer structure may be inadvertently turned on by incident ionizing radiation which generates photocurrent in the base region of the npn transistor. Alternatively, for example, current may be supplied by temporary voltage conditions caused by transient over- and undershoot-voltage or by power supply turn-on sequences. Specifically, protective gate diodes are troublesome as a source of current in that they are intended to bypass excessive voltages on the gate electrode.
The problem of parasitic pnpn structures causing latch-up in CMOS integrated circuits was described in a paper entitled "Latch-up in CMOS Integrated Circuits" by B. L. Gregory and B. D. Shafer published in IEEE Trans. Nuc. Sci., NS-20, No. 6, pp. 293-299 in December 1973. Parasitic pnpn structures were found to exist in two CMOS circuits RCA-type CD4007A and CD4041A, which could be induced to the low resistance state by radiation-induced photocurrent. Methods for preventing latch-up of CMOS circuits were suggested such as by varying the material parameters, varying the circuit layout and varying the CMOS processing. Specifically, B. L. Gregory et al. suggests reducing the lifetime of the material such that the product of the npn and pnp common emitter current gains (h.sub.fe) are less than unity. Transient radiation studies on circuits having reduced lifetime material confirm the absence of latch-up.
Presently, to prevent latch-up through the parasitic pnpn structures in integrated circuits, various techniques are employed. The lifetime of the minority carriers in a substrate are reduced throughout the substrate by gold diffusion; doped regions are isolated by dielectric isolation; and the integrated circuit layout is varied to minimize photocurrent generation in the p regions and voltage drops in the n regions by providing heavily doped layers to provide low resistance paths. However, all of these methods involve variations in the design of the circuits manufactured for non-radiation environments which, in turn, implies additional processing steps in the device fabrication. Also, some of the processing steps such as gold doping in particular are difficult to control precisely which could result in lower circuit yields.
A technique for reducing the switching time of semiconductor devices such as thyristors, triacs, diacs, reverse switching rectifier and reverse conducting thyristors by nuclear irradiation is described in U.S. Pat. No. 4,056,408 issued on Nov. 1, 1977 to John Bartko, one of the co-inventors herein, and Kuan H. Sun and assigned to the assignee herein. In U.S. Pat. No. 4,056,408 the switching time of thyristors is reduced by irradiating the blocking pn junction with particles having a molecular weight of at least one to provide maximum defect generation adjacent to the pn junction preferably in the impurity or doped region of higher impurity concentration. A radiation source of monoenergetic particles with molecular weight of at least one may be provided by a Van de Graaff accelerator.
The nature of defect generation in silicon by proton radiation has been investigated experimentally by Y. V. Bugakov and T. I. Kolomenskaya, Soviet Physics-Semiconductors 1, 346 (1967) and the nature of defect generation by proton, deuteron and alpha irradiation has been predicted theoretically by Y. V. Bugakov and M. A. Kumakhov, Soviety Physics-Semiconductors 2, 1334 (1968). These analyses demonstrated that the defect generation by such nuclear radiation is concentrated in relatively narrow regions near the end of the particle penetration into the material such as silicon.
It is therefore desirable to eliminate latch-up or the turning on to a high conductance state of parasitic pnpn structures induced by transient ionizing radiation.
It is further desirable to modify the parameters of a pnpn structure such that the product of the npn and pnp transistor gains is less than one.
It is further desirable to irradiate integrated circuits to provide low lifetime regions.
It is further desirable to irradiate semiconductor circuits to provide regions of high trap density.
It is further desirable to irradiate with monoenergetic ions to produce narrow regions of high displacement, vacancy-interstitial pairs which will result in the formation of traps.
It is further desired to provide a metal mask over a circuit to be irradiated to control the width of the selected regions for exposure to ions.